#====================================== #step 1: logical library settings #====================================== #set SEARCH_PATH"/home/xiaff/ftp" #set TARGET_LIBRARY_FILES IC05CScore_33_typ.db #set LINK_LIBRARY_FILES IC05CScore_33_typ.db #set SYMBOL_LIBRARY_F ...
//source the fsm_moore.tcl and print the process to terminal compile.log redirect -tee -file ${WORK_PATH}/compile.log {source -echo -verbose fsm_moore.tcl} //把{source -echo -verbose fsm_moore.tcl}脚本执行的结果放在compile.log
//step 1: read elaborate the RTL file list set TOP_MODULE top analze -format verilog elaborate$TOP_MODULE -architecture verilog current_desin $TOP_MODULE if { ==0}{ echo "link with error!"; exit; }; if { ==0}{ echo "check design with error!"; exit; }; //ste ...
module UART_XMTR #(parameter word_size=8)( output Serial_out, input Data_Bus, inputLoad_XMT_datareg,Byte_ready,T_byte,Clock,rst_b ); Control_Unit M0(Load_XMT_DR,Load_XMT_shftreg,start,clear, ...
//UART接收器 module UART_RCVR #(parameter word_size=8,half_word=word_size/2)( output RCV_datareg, outputread_not_ready_out,Error1,Error2, inputSerial_in,read_not_ready_in, ...
//sha256 20180801 `timescale 1ns/1ns module SHA2560801 #(parameter SIZE=16)(data,zhaiyao,rst_n,n,clk); input data; inputrst_n; inputclk; input n;//输入数据的位数,用64位数据表示 output reg zhaiyao; //得到 ...
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