0. Systemverilog standard 0.1. IEEE Std 1800-2005 0.2. IEEE Std 1800-2009 0.3. IEEE Std 1800-2012 1. Packed Array and Unpacked Array bit B; ...
1. regression list process 1.1 each line shall chop the "\t" and space in the beginning and end. 1.2 leave only one space between two words. 2. perl5: 2.1 perl5 support OOP with "package" 2.2 or比||优先级低 & ...
1. combinational UDP primitive tsmc_mux (q, do, d1, s); output q; input do, d1, s; table //d0, d1, s: q 0 ? 0 : 0; 1 ? 0 : 1; ? 0 1 : 0; ? 1 1 : 1; 0 0 x : 0; 1 1 x: 1; endtable endprimitive ...
一般interface protocol把component分为master, slave Master: 发起transaction slave: 对transaction产生response 从是否驱动DUT的角度,可以分为: active:驱动DUT信号 (Driver){agent会有driver, monitor, sequencer} passive: 只监听DUT信号 ( ...
1. 3-step flow -- for mixed vhdl and verilog language vhdlan -f vhdl_file_list vlogan uvm // need to compile uvm independently vlogan -f rtl_file_list simv
class my_driver # ( int data_width = 32 ) extends uvm_driver # ( my_seq_item ) ; protected virtual my_interface # ( data_width ) my_vif ; //... endclass class my_agent # ( int data_width = 32 ) extends uvm_agent ; my_driver # ( data_ ...
interface param_if#(int width = 8); logic clk; logic data; clocking active_cb @(posedge clk); default input #1 output #1; output data; endclocking   ...
象下面用继承+factory实现callback的方法,导致unmanageable explosion of driver class class driver extends uvm_driver #(packet); `uvm_component_utils(driver) function new(string name, uvm_component parent); super.new(name, parent); & ...
dve has interactive mode and post-process mode: interactive mode: start dve and control simulator (vcs) to run 1. simv -gui 2. simv -ucli 3. vcs -gui -R 4. dve -toolexe name -toolargs simulator args post-process mode: run simulation and use dve to check waveform. or coverage ...
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