1. setup time 如何计算? 2. hold time 如何计算?
1. 三态门应该怎样设计? 2. 为什么CMOS latch使用传输门结构,而不实用本科学习的双与门结构? 3. latch 用于 timing borrowing 4. lock up latch
1. Directed Verification - Random Verification 1.1 Directed Verification testcase生成stimulus, Env把stimulus发送给DUT, 并收集DUT的response并检测; directed verification 也会使用一定的randomization(通常针对data) 每个t ...
class Eth_rx ; rand integer Pkt_len ; rand integer Var ; constraint var_c { Var 1518 ; Var 64 ;} endclass program Eth_25 ; Eth_rx rx = new (); initial begin rx . Pkt_len = 32 ; rx . Var ...
1. in DC, use "report_loop" 2. Linting 3. vcs 3.1 compile, evaluation and simv otpion vcs +vcs+loopdetect ... 3.2 ucli interface: use loop_detect.tcl in the hanging point #!/usr/bin/tclsh proc loop_detect {args} { set h ...
0 Verilog History 0.1. IEEE Std 1364-1995 0.2. IEEE std 1364-2001 0.3. IEEE std 1364-2005 1. 如何加pullup rtranif1 (port0, vdd_pull1, en); 注意:assign (pull1, pull0) port0 = en ? 1'b1 : 1' ...
1. add monitor on all pad, to make sure no 'z on pad. RTL don't have issue, but GLS will fail since x propogation
1. Cadence: cpf 2. synopsys: upf 2.1 旧的工具:mvrc 2.2 新的工具:VCLP 3. LVT: 低阈值,延迟小,静态功耗大,常用于修复setup timing violation RVT: 正常阈值,synthesis和PR时最常使用的cell HVT: 高阈值,延迟大,静 ...
1. 2018版本以后, 使用“-kdb" 2. 2018版本以前,使用“-P novas.tab”
reset 是异步信号, uvm 处理会 比较麻烦
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