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状态机的一个经典实例:
module fsm(clk,reset,out);
input clk,reset;
output out;
reg [1:0] current_state, next_state;
reg out;
parameter [1:0] idle = 2'b00,
s1 = 2'b01,
s2 = 2'b10,
s3 = 2'b11;
always @(posedge clk )
if (~reset)
current_state = idle;
else
current_state = next_state;
always @(current_state )
begin
next_state = current_state;//这一句有什么作用啊?
case (current_state)
idle: begin
next_state = s1;
out = 0;
end
s1:begin
next_state = s2;
out = 1;
end
s2:begin
next_state = s3;
out = 1;
end
s3:begin
next_state = idle;
out = 1;
end
default:next_state = idle;
endcase
end
endmodule