module MUX32_1(sel32, i32, o32)

begin

input [4:0] sel32;

input [31:0] i32;

output  o32;

wire [7:0] a;

wire [1:0] b;

MUX4_1 U0 ( .sel4(sel32[1:0]), .i4(i32[ 3: 0]), .o4(a[0]) );

MUX4_1 U1 ( .sel4(sel32[1:0]), .i4(i32[ 7: 4]), .o4(a[1]) );

MUX4_1 U2 ( .sel4(sel32[1:0]), .i4(i32[11: 8]), .o4(a[2]) );

MUX4_1 U3 ( .sel4(sel32[1:0]), .i4(i32[15:12]), .o4(a[3]) );

MUX4_1 U4 ( .sel4(sel32[1:0]), .i4(i32[19:16]), .o4(a[4]) );

MUX4_1 U5 ( .sel4(sel32[1:0]), .i4(i32[23:20]), .o4(a[5]) );

MUX4_1 U6 ( .sel4(sel32[1:0]), .i4(i32[27:24]), .o4(a[6]) );

MUX4_1 U7 ( .sel4(sel32[1:0]), .i4(i32[31:28]), .o4(a[7]) );

assign b[0] = sel32[2] ? a[4] : a[1];

assign b[1] = sel32[2] ? a[7] : a[0];

assign b[2] = sel32[2] ? a[5] : a[2];

assign b[3] = sel32[2] ? a[6] : a[3];

MUX4_1 U8 (.sel4(sel32[4:3]), .i4(b[3:0]), .o4(o32) );

endmodule

/********  sub module ********/

module MUX4_1(sel4, i4, o4)

begin

input  [1:0] sel4;

input  [3:0] i4;

output  o4;

always @(*)

    case(sel4):

      2’b00: o4 = i4 [0];

      2’b01: o4 = i4 [1];

      2’b10: o4 = i4 [2];

      2’b11: o4 = i4 [3];

    endcase

endmodule