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ESD(9)

已有 3095 次阅读| 2006-8-26 10:03

天气: 晴朗
心情: 高兴

第十章 結 論

  ESD防護技術隨著CMOS製程的先進演變而越來越困

難,然而世界先進國家的各大IC廠商在ESD防護上的研究

更趨熱烈,各式各樣的技術都被嘗試用在ESD防護上,因

而已有六百多件ESD相關的美國專利已刊登出來。本文乃

就各種可能的技術中,介紹在CMOS製程技術下較實用可

行的ESD防護設計給IC相關設計者一個概念,但是在產品

商業化時,要注意專利的智慧財產權問題。大多數的ESD

設計都已有專利或者專利申請中,因其實在是高難度的設

計工作。

  ESD的防護設計除了本文所談的技術之外,另外要注

意整顆積體電路的ESD防護架構。ESD的防護是整顆積體

電路的問題,而不只是Input PAD,Output PAD,或 Power

PAD的問題,即使各個PAD都有很好的ESD防護能力,不

見得整顆積體電路就有很高的ESD防護能力。採用適當的

全晶片(whole-chip)防護架構設計,才能真正提昇整顆積體

電路的ESD防護能力,並且可以節省I/O PAD上ESD防護元

件的尺寸與佈局面積。全晶片ESD防護架構已經是目前各

大公司專利競逐的焦點所在,對此技術未有警覺性的公司

要特別注意這項技術的發展。

REFERENCES
  1. MIL-STD-883C method 3015.7, "Military Standard Test Methods and Proc. For Microelectronics", Dept. of Defense, Washington, D. C., U.S.A., 1989.

  2. C. H. Dfaz, T. E. Kopley, and P. J. Marcoux, "Building-in ESD/EOS reliability for Sub-Halfmicron CMOS Processes," IEEE Transactions on Electron Devices, Vol. 43, No. 6, pp. 991-999, June 1996.

  3. Ming-Dou Ker and Tain-Shun Wu, "ESD Protection for Submicron CMOS IC’s—A Tutorial,” CCL Technical Journal, Vol. 42, pp. 10-24, Sept. 1995

  4. T. J. Maloney and N. Khurana, "Transmission Line Plising Techniques for Circuit Modeling of ESD Phenomena, " EOS/ESD Symposium Proceedings, EOS-7, pp. 49-54, 1985.

  5. C. Duvvury, R. N. Rountree, and O. Adams, "Internal chip ESD phenomena beyond the protection circuit," IEEE Trans. on Electron Devices, vol. 35, pp.2133-2139, Dec., 1988.

  6. M. D. Jaffe and P. E. Cottrell, "Electrostatic discharge protection in a 4-Mbit DRAM," EOS/ESD Symp. Proc., 1990, EOS-12, pp.218-223.

  7. C. C. Johnson, T. J. Maloney, and S. Qawami, "Two unusual HBM ESD failure mechanisms on a mature CMOS process," EOS/ESD failure mechanisms on a mature CMOS process," EOS/ESD Symp. Proc., 1993, EOS-15, pp.225-231.

  8. H. Terletzki, W. Nikutta, and W. Reczek, "Influence of the series resistance of on-chip power supply buses on internal device failure after ESD stress," IEEE Trans. on Electron Devices, vol. 40, pp. 2081-2083, Nov., 1993.

  9. C.-N. Wu, M.-D. Ker, et al., "Unexpected ESD damage on internal circuits of sub-μm CMOS technology," Proc. of International Electron Devices and Materials Symposium, 1996, pp.143-146.

  10. EOS/ESD Standard for ESD Sensitivity Testing, EOS/ESD Association, NY., 1993.

  11. C. Cook and S. Daniel, "Characterization of new failure mechanisms arising from power-pin ESD stressing," EOS/ESD Symp. Proc., 1993, EOS-15, pp. 149-156.

  12. M.-D. Ker and S.-C. Liu, "Whole-chip ESD protection design for submicron CMOS VLSI," Proc. of IEEE International Symposium on Circuits and Systems, pp. 1920-1923, 1997.

  13. R. Merrill and E. Issaq, "ESD design methodology,"  EOS/ESD Symp. Proc., 1993, EOS-15, PP. 233-237.

  14. E. R. Worley, et al., "ESD protection for submicron CMOS circuits", US Patent#5440162, 1995.

  15. E. R. Worley, et al., "Sub-micron chip ESD protection schemes which avoid avalanching junctions," EOS/ESD Symp. Proc., 1995, EOS-17, pp. 13-20.

  16. S. Dabral, R. Aslett, and T. Maloney, "Core clamps for low voltage technologies," EOS/ESD Symp. Proc., 1994, EOS-16, pp. 141-149.

  17. W. Miller, "Electrostatic discharge detection and clamp control circuits," U.S. Patent #5255146, 1993.

  18. T. Dungan and E. Coussens, "Electrostatic discharge protection circuit with dynamic triggering," US Patent #5311391, 1994.

  19. G. D. Croft, "ESD protection using a variable voltage supply clamp," EOS/ESD Symp. Proc., 1994, EOS-16, PP. 135-140.

  20. J. T. Watt and A. J. Walker, "A hot-carrier triggered SCR for smart power bus ESD protection," 1995 IEDM Technical Digest, pp. 341-344.

  21. T. Maloney and S. Dabral, "Novel clamp circuits for IC power supply protection," EOS/ESD Symp. Proc., 1995, EOS-17, PP. 1-12.

  22. M.-D Ker, "Area-efficient VDD-to-VSS ESD clamp circuit by using substrate-triggering field-oxide device (STFOD) for whole-chip ESD protection," Proc. of International Symposium on VLSI Technology, Systems, and Applications, pp. 69-73, 1997.

  23. M.-D. Ker, T.-Y. Chen, and C.-Y. Wu, "Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC's with the substrate-triggering technique," Proc. of IEEE International ASIC Conference & Exhibits, pp. 287-290, 1997.

  24. M.-D. Ker  and T.-L. Yu, "ESD protection to overcome internal gate-oxide damage on digital-analog interface of mixed-mode CMOS IC's," Proc. of European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, pp.1727-1730, 1996.

  25. M.-D. Ker, C.-Y. Wu, H.-H. Chang, and T.-S. Wu, "Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicon CMOS technology," Proc. of IEEE Custom Integrated Circuits Conference, pp. 31-34, 1997.

 

 


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回复 led_hksp 2010-1-19 17:40
very good!

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