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xilinx_ioserdes

上一篇 / 下一篇  2018-08-09 23:30:41 / 个人分类:FPGA_Verilog

`timescale 1ps/1ps
module tb;

//----------------------------------------------------------------------------//
//parameter CLK_CY_25M = 40*1000;
parameter CLK_CY_50M = 20*1000;
//parameter CLK_CY_66M = 15*1000;
parameter CLK_CY_100M = 10*1000;
//parameter CLK_CY_125M = 8*1000;
//parameter CLK_CY_200M = 5*1000;
//parameter CLK_CY_600M = 1666;


//bit clk_25m;
bit clk_50m;
//bit clk_66m;
bit clk_100m = 1'b1;
//bit clk_200m;
//bit clk_600m;
//always #(CLK_CY_25M/2) clk_25m = ~clk_25m;
always #(CLK_CY_50M/2) clk_50m = ~clk_50m;
//always #(CLK_CY_66M/2) clk_66m = ~clk_66m;
always #(CLK_CY_100M/2) clk_100m = ~clk_100m;
//always #(CLK_CY_200M/2) clk_200m = ~clk_200m;
//always #(CLK_CY_600M/2) clk_600m = ~clk_600m;
//----------------------------------------------------------------------------//

//----------------------------------------------------------------------------//
bit rst_n;
initial
begin
    rst_n = 1'b1;
    #(CLK_CY_100M * 300) rst_n = 1'b0;
    #(CLK_CY_100M * 300) rst_n = 1'b1;
end
//----------------------------------------------------------------------------//
reg                 bit_slip;
wire                tx_dat_ser;
wire    [3:0]       rx_dat_pal;
reg     [7:0]       cnt_cal;
always @ (posedge clk_50m or negedge rst_n)
begin
    if (rst_n == 1'b0)
        cnt_cal <= 8'd0;
    else if (cnt_cal < 8'd255)
        cnt_cal <= cnt_cal + 8'd1;
    else ;
end

reg     [3:0]       tx_dat;
always @ (posedge clk_50m or negedge rst_n)
begin
    if (rst_n == 1'b0)
        tx_dat <= 4'd0;
    else if (cnt_cal < 8'd255)
        tx_dat <= 4'd3;
    else
        tx_dat <= tx_dat + 4'd1;
end

always @ (posedge clk_50m or negedge rst_n)
begin
    if (rst_n == 1'b0)
        bit_slip <= 1'b0;
    else if (cnt_cal < 8'd255)
    begin
        if (cnt_cal[3:0] == 4'd15) begin
            if (rx_dat_pal != 4'd3)
                bit_slip <= 1'b1;
            else ;
        end
        else
            bit_slip <= 1'b0;
    end
    else ;
end


OSERDESE2 #(
   .DATA_RATE_OQ("DDR"),   // DDR, SDR
   .DATA_RATE_TQ("DDR"),   // DDR, BUF, SDR
   .DATA_WIDTH(4),         // Parallel data width (2-8,10,14)
   .INIT_OQ(1'b0),         // Initial value of OQ output (1'b0,1'b1)
   .INIT_TQ(1'b0),         // Initial value of TQ output (1'b0,1'b1)
   .SERDES_MODE("MASTER"), // MASTER, SLAVE
   .SRVAL_OQ(1'b0),        // OQ output value when SR is used (1'b0,1'b1)
   .SRVAL_TQ(1'b0),        // TQ output value when SR is used (1'b0,1'b1)
   .TBYTE_CTL("FALSE"),    // Enable tristate byte operation (FALSE, TRUE)
   .TBYTE_SRC("FALSE"),    // Tristate byte source (FALSE, TRUE)
   .TRISTATE_WIDTH(4)      // 3-state converter width (1,4)
)
OSERDESE2_a (
   .OFB(),             // 1-bit output: Feedback path for data
   .OQ(tx_dat_ser),               // 1-bit output: Data path output
   // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
   .SHIFTOUT1(),
   .SHIFTOUT2(),
   .TBYTEOUT(),   // 1-bit output: Byte group tristate
   .TFB(),             // 1-bit output: 3-state control
   .TQ(),               // 1-bit output: 3-state control
   .CLK(clk_100m),             // 1-bit input: High speed clock
   .CLKDIV(clk_50m),       // 1-bit input: Divided clock
   // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
   .D1(tx_dat[0]),
   .D2(tx_dat[1]),
   .D3(tx_dat[2]),
   .D4(tx_dat[3]),
   .D5(1'b0),
   .D6(1'b0),
   .D7(1'b0),
   .D8(1'b0),
   .OCE(1'b1),             // 1-bit input: Output data clock enable
   .RST(~rst_n),             // 1-bit input: Reset
   // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
   .SHIFTIN1(1'b0),
   .SHIFTIN2(1'b0),
   // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
   .T1(1'b0),
   .T2(1'b0),
   .T3(1'b0),
   .T4(1'b0),
   .TBYTEIN(1'b0),     // 1-bit input: Byte group tristate
   .TCE(1'b1)              // 1-bit input: 3-state clock enable
);



ISERDESE2 #(
   .DATA_RATE("DDR"),           // DDR, SDR
   .DATA_WIDTH(4),              // Parallel data width (2-8,10,14)
   .DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
   .DYN_CLK_INV_EN("FALSE"),    // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
   // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
   .INIT_Q1(1'b0),
   .INIT_Q2(1'b0),
   .INIT_Q3(1'b0),
   .INIT_Q4(1'b0),
   .INTERFACE_TYPE("NETWORKING"),   // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
   .IOBDELAY("IFD"),           // NONE, BOTH, IBUF, IFD
   .NUM_CE(2),                  // Number of clock enables (1,2)
   .OFB_USED("FALSE"),          // Select OFB path (FALSE, TRUE)
   .SERDES_MODE("MASTER"),      // MASTER, SLAVE
   // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
   .SRVAL_Q1(1'b0),
   .SRVAL_Q2(1'b0),
   .SRVAL_Q3(1'b0),
   .SRVAL_Q4(1'b0)
)
ISERDESE2_q_l (
   .O(),                       // 1-bit output: Combinatorial output
   // Q1 - Q8: 1-bit (each) output: Registered data outputs
   .Q1(rx_dat_pal[3]),
   .Q2(rx_dat_pal[2]),
   .Q3(rx_dat_pal[1]),
   .Q4(rx_dat_pal[0]),
   .Q5(),
   .Q6(),
   .Q7(),
   .Q8(),
   // SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
   .SHIFTOUT1(),
   .SHIFTOUT2(),
   .BITSLIP(bit_slip),           // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
                                // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
                                // to Q8 output ports will shift, as in a barrel-shifter operation, one
                                // position every time Bitslip is invoked (DDR operation is different from
                                // SDR).

   // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
   .CE1(1'b1),
   .CE2(1'b1),
   .CLKDIVP(1'b0),           // 1-bit input: TBD
   // Clocks: 1-bit (each) input: ISERDESE2 clock input ports
   .CLK(clk_100m),                   // 1-bit input: High-speed clock
   .CLKB(~clk_100m),// 1-bit input: High-speed secondary clock
   .CLKDIV(clk_50m),             // 1-bit input: Divided clock
   .OCLK(1'b0),                 // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
   // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
   .DYNCLKDIVSEL(1'b0), // 1-bit input: Dynamic CLKDIV inversion
   .DYNCLKSEL(1'b0),       // 1-bit input: Dynamic CLK/CLKB inversion
   // Input Data: 1-bit (each) input: ISERDESE2 data input ports
   .D(1'b0),                       // 1-bit input: Data input
   .DDLY(tx_dat_ser),                 // 1-bit input: Serial data from IDELAYE2
   .OFB(1'b0),                   // 1-bit input: Data feedback from OSERDESE2
   .OCLKB(1'b0),               // 1-bit input: High speed negative edge output clock
   .RST(~rst_n),                   // 1-bit input: Active high asynchronous reset
   // SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
   .SHIFTIN1(1'b0),
   .SHIFTIN2(1'b0)
);

endmodule


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