`timescale 1ns/1ps
module tb_clk_drp;
parameter CLK_CY_100M = 10;
bit clk_100m;
always #(CLK_CY_100M/2) clk_100m = ~clk_100m;
//----------------------------------------------------------------------------//
//----------------------------------------------------------------------------//
bit rst_n;
initial
begin
rst_n = 1'b1;
#(CLK_CY_100M * 200) rst_n = 1'b0;
#(CLK_CY_100M * 100) rst_n = 1'b1;
end
//----------------------------------------------------------------------------//
reg [31:0] rd_dat;
reg [10:0] s_axi_awaddr;
reg s_axi_awvalid;
wire s_axi_awready;
reg [31:0] s_axi_wdata;
reg [3:0] s_axi_wstrb;
reg s_axi_wvalid;
wire s_axi_wready;
wire [1:0] s_axi_bresp;
wire s_axi_bvalid;
reg s_axi_bready;
reg [10:0] s_axi_araddr;
reg s_axi_arvalid;
wire s_axi_arready;
wire [31:0] s_axi_rdata;
wire [1:0] s_axi_rresp;
wire s_axi_rvalid;
reg s_axi_rready;
initial begin
s_axi_awaddr = 11'd0;
s_axi_awvalid = 1'd0;
s_axi_wdata = 32'd0;
s_axi_wstrb = 4'd15;
s_axi_wvalid = 1'b0;
s_axi_bready = 1'b0;
s_axi_araddr = 11'd0;
s_axi_arvalid = 1'b0;
s_axi_rready = 1'b0;
end
task axi_wr(input [10:0] awaddr, input [31:0] wdata);
begin
@ (posedge clk_100m)
s_axi_awvalid = 1'b1;
s_axi_wvalid = 1'b1;
s_axi_wdata = wdata;
s_axi_awaddr = awaddr;
s_axi_wstrb = 4'hf;
s_axi_bready = 1'b0;
wait (s_axi_wready && s_axi_awready)
@ (posedge clk_100m)
s_axi_bready = 1'b1;
wait (s_axi_bvalid)
@ (posedge clk_100m)
s_axi_awvalid = 1'b0;
s_axi_wvalid = 1'b0;
s_axi_bready = 1'b0;
end
endtask
task axi_rd(input [10:0] araddr, output [31:0] rd_dat);
begin
@ (posedge clk_100m)
s_axi_arvalid = 1'b1;
s_axi_rready = 1'b1;
s_axi_araddr = araddr;
wait (s_axi_rvalid)
rd_dat = s_axi_rdata;
@ (posedge clk_100m)
s_axi_arvalid = 1'b0;
s_axi_rready = 1'b0;
end
endtask
initial begin
repeat(500) @ (posedge clk_100m);
//read mmcm cfg
axi_rd(11'h208, rd_dat);
repeat(30) @ (posedge clk_100m);
axi_rd(11'h20c, rd_dat);
repeat(30) @ (posedge clk_100m);
axi_rd(11'h210, rd_dat);
repeat(30) @ (posedge clk_100m);
//write new cfg to mmcm
axi_wr(11'h208, 32'h0004_0014);
repeat(30) @ (posedge clk_100m);
axi_wr(11'h20c, 32'h0000_0000);
repeat(30) @ (posedge clk_100m);
axi_wr(11'h210, 32'h0000_c350);
repeat(30) @ (posedge clk_100m);
axi_wr(11'h25c, 32'h0000_0003);
repeat(10) @ (posedge clk_100m);
repeat(2000) @ (posedge clk_100m);
$stop;
end
clk_recfg u_clk_recfg
(
.s_axi_aclk (clk_100m ),
.s_axi_aresetn (rst_n ),
.s_axi_awaddr (s_axi_awaddr ),
.s_axi_awvalid (s_axi_awvalid ),
.s_axi_awready (s_axi_awready ),
.s_axi_wdata (s_axi_wdata ),
.s_axi_wstrb (s_axi_wstrb ),
.s_axi_wvalid (s_axi_wvalid ),
.s_axi_wready (s_axi_wready ),
.s_axi_bresp (s_axi_bresp ),
.s_axi_bvalid (s_axi_bvalid ),
.s_axi_bready (s_axi_bready ),
.s_axi_araddr (s_axi_araddr ),
.s_axi_arvalid (s_axi_arvalid ),
.s_axi_arready (s_axi_arready ),
.s_axi_rdata (s_axi_rdata ),
.s_axi_rresp (s_axi_rresp ),
.s_axi_rvalid (s_axi_rvalid ),
.s_axi_rready (s_axi_rready ),
.clk_out1 (),
.locked (),
.clk_in1 (clk_100m)
);
endmodule