module decode16
(
input rst,
input clk,
input [15:0] din,
output reg [3:0] addr
);
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
addr <= 4'd0;
else
begin
case (din)
16'h0001: addr <= 4'd0;
16'h0002: addr <= 4'd1;
16'h0004: addr <= 4'd2;
16'h0008: addr <= 4'd3;
16'h0010: addr <= 4'd4;
16'h0020: addr <= 4'd5;
16'h0040: addr <= 4'd6;
16'h0080: addr <= 4'd7;
16'h0100: addr <= 4'd8;
16'h0200: addr <= 4'd9;
16'h0400: addr <= 4'd10;
16'h0800: addr <= 4'd11;
16'h1000: addr <= 4'd12;
16'h2000: addr <= 4'd13;
16'h4000: addr <= 4'd14;
16'h8000: addr <= 4'd15;
default: addr <= 4'd0;
endcase
end
end
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module decode128
(
input rst,
input clk,
input [127:0] din,
output reg [6:0] addr
);
reg [3:0] addr_l4[7:0];
genvar i;
generate
for (i=0;i<8;i=i+1)
begin: DECODE_GRP
decode16 u_decode16
(
.rst (rst),
.clk (clk),
.din (din[(i+1)*16-1:i*16]),
.addr (addr_l4[i])
);
end
endgenerate
reg [7:0] addr_grp;
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
addr_grp <= 8'h00;
else
begin
addr_grp[0] <= | din[15:0];
addr_grp[1] <= | din[31:16];
addr_grp[2] <= | din[47:32];
addr_grp[3] <= | din[63:48];
addr_grp[4] <= | din[79:64];
addr_grp[5] <= | din[95:80];
addr_grp[6] <= | din[111:96];
addr_grp[7] <= | din[127:112];
end
end
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
addr <= 7'd0;
else
begin
case (addr_grp)
8'h01: addr <= {3'd0,addr_l4[0]} + 7'd0;
8'h02: addr <= {3'd0,addr_l4[1]} + 7'd16;
8'h04: addr <= {3'd0,addr_l4[2]} + 7'd32;
8'h08: addr <= {3'd0,addr_l4[3]} + 7'd48;
8'h10: addr <= {3'd0,addr_l4[4]} + 7'd64;
8'h20: addr <= {3'd0,addr_l4[5]} + 7'd80;
8'h40: addr <= {3'd0,addr_l4[6]} + 7'd96;
8'h80: addr <= {3'd0,addr_l4[7]} + 7'd112;
default: addr <= 7'd0;
endcase
end
end
endmodule