`timescale 1ns/1ns

module alt_gxb_ch
    (
    input                   clk_50m,
    input                   clk_125m,
    input                   rst_clk_50m,
    input                   rst_clk_125m,
    input                   pll_inclk,
    input                   rst,
    input                   gxb_channel_rst,
    input                   gxb_pwr_dn,                     //gxb power down control, high active
    input           [7:0]   tx_data_in,                     //parallel data in, low speed
    input                   tx_data_syn,                    //parallel data in syn, high active
    input                   rx_data_in,                     //serial data in, high speed

    output          [7:0]   rx_data_out,                    //parallel data out, low speed
    output                  rx_data_syn,                    //parallel data out syn, low speed

    output                  tx_data_out                     //serial data out, high speed

    );

wire            rx_pll_locked;
wire            rx_freq_locked;
wire            lock_to_data;
wire            lock_to_refclk;
wire            pll_locked;
wire            tx_digital_rst;
wire            rx_analog_rst;
wire            rx_digital_rst;
wire            rx_clk;
wire            tx_clk;
wire            pll_locked;
wire            rst_tx_clk;
wire            rst_rx_clk;
wire    [8:0]   tx_data;
wire    [7:0]   gxb_rx_data;
wire            gxb_rx_data_syn;

alt_gxb_clk_ctrl    u_alt_gxb_clk_ctrl
    (
    .rst(rst_clk_125m),
    .clk(clk_125m),

    .rx_pll_locked(rx_pll_locked),
    .rx_freq_locked(rx_freq_locked),

    .lock_to_data(lock_to_data),
    .lock_to_refclk(lock_to_refclk)
    );

alt_gxb_pwdn_rst_ctrl   u_alt_gxb_pwdn_rst_ctrl
    (
    .clk_50m(clk_50m),
    .rst_clk_50m(rst_clk_50m),

    .gxb_power_down(gxb_pwr_dn),
    .gxb_channel_rst(gxb_channel_rst),
    .pll_locked(pll_locked),
    .rx_pll_locked(rx_pll_locked),
    .rx_freq_locked(rx_freq_locked),

    .tx_digital_rst(tx_digital_rst),
    .rx_analog_rst(rx_analog_rst),
    .rx_digital_rst(rx_digital_rst)

    );

rst_ctrl    u0_rst_ctrl
    (
    .clk(tx_clk),
    .rst(rst),

    .rst_prc(rst_tx_clk)
    );

rst_ctrl    u1_rst_ctrl
    (
    .clk(rx_clk),
    .rst(rst),

    .rst_prc(rst_rx_clk)
    );

asyn_fifo
    #(
   .DATA_WIDTH(9),
   .FIFO_DEPTH(16)

    )u_tx_asyn_fifo
    (
    .rst_clk_wr(rst_clk_125m),
    .rst_clk_rd(rst_tx_clk),
    .clk_wr(clk_125m),
    .data_wr({tx_data_syn,tx_data_in}),
    .clk_rd(tx_clk),

    .data_rd(tx_data)
    );

asyn_fifo
    #(
   .DATA_WIDTH(9),
   .FIFO_DEPTH(16)

    )u_rx_asyn_fifo
    (
    .rst_clk_wr(rst_rx_clk),
    .rst_clk_rd(rst_clk_125m),
    .clk_wr(rx_clk),
    .data_wr({gxb_rx_data_syn,gxb_rx_data}),
    .clk_rd(clk_125m),

    .data_rd({rx_data_syn,rx_data_out})
    );

alt_gxb u_alt_gxb
    (
    //input
 .cal_blk_clk(clk_50m),
 .gxb_powerdown(gxb_pwr_dn),
 .pll_inclk(pll_inclk),
 .rx_analogreset(rx_analog_rst),
 .rx_datain(rx_data_in),
 .rx_digitalreset(rx_digital_rst),
 .rx_locktodata(lock_to_data),
 .rx_locktorefclk(lock_to_refclk),
 .tx_ctrlenable(tx_data[8]),
 .tx_datain(tx_data[7:0]),
 .tx_digitalreset(tx_digital_rst),
 //output
 .pll_locked(pll_locked),
 .rx_clkout(rx_clk),
 .rx_ctrldetect(gxb_rx_data_syn),
 .rx_dataout(gxb_rx_data),
 .rx_disperr(),
 .rx_errdetect(),
 .rx_freqlocked(rx_freq_locked),
 .rx_pll_locked(rx_pll_locked),
 .tx_clkout(tx_clk),
 .tx_dataout(tx_data_out)
 );

endmodule