The target_library variable specifies the library that Design Compiler
uses to select cells for optimization and re-mapping. It is typically set
to only the standard cells library.

The link_library variable specifies every library that has cells referenced
by the netlist. The tool uses the libraries specified in the link_library
variable for resolving references (linking). The link_library can include
memory (RAM, ROM or any macro) libraries, in addition to the standard cell
library. For example,

set synthetic_library "dw_foundation.sldb"
set target_library "gates.db"
set link_library "* $synthetic_library $target_library io.db rams.db"

The "*" stands for all designs that have already been loaded into
Design Compiler. The synthetic_library variable specifies the
DesignWare library, which contains more complex cells.

The input design files for Design Compiler are often written using a
hardware description language (HDL) such as Verilog or VHDL.
Design Compiler uses technology libraries, synthetic or DesignWare
libraries during the synthesis process.

During the synthesis process, Design Compiler translates the HDL
description to components extracted from the generic technology
(GTECH) library and DesignWare library. The GTECH library consists
of basic logic gates and flip-flops. The DesignWare library contains
more complex cells such as adders and comparators. Both the GTECH and
DesignWare libraries are technology independent, that is, they are not
mapped to a specific technology library.

After translating the HDL description to gates, Design Compiler
optimizes and maps the design to a specific technology library,
known as the target library. The process is constraint driven.
Constraints are the designer's specification of timing and
environmental restrictions under which synthesis is to be performed.

Design Compiler uses the link library to resolve references. For a
design to be complete, it must connect to all the library components
and designs it references. This process is called linking the design or
resolving references.