module divfreq(clk, clk1x, rst, clk1xpose, clk1xnege, coutpose, coutnege);

input clk;
input rst;
output clk1x;
output clk1xpose;
output clk1xnege;
output[2:0] coutpose;
output[2:0] coutnege;

reg clk1xpose;
reg clk1xnege;
reg[2:0] coutpose;
reg[2:0] coutnege;

parameter div1 = 2 , div2 = 4;  // div1 ＝ 5 / 2, div2 = 5 - 1

assign clk1x = clk1xpose | clk1xnege;

always@(posedge clk or negedge rst)
 begin
  if(!rst)
 
    clk1xpose = 0;
 
  else if(coutpose == div1)
    clk1xpose = ~clk1xpose;
  else if(coutpose == div2)
    clk1xpose = ~clk1xpose;
  else
    clk1xpose = clk1xpose;
 end

always@(negedge clk or negedge rst)
 begin
  if(!rst)
 
    clk1xnege = 0;
 
  else if(coutnege == div1)
   clk1xnege = ~clk1xnege;
  else if(coutnege == div2)
   clk1xnege = ~clk1xnege;
  else
   clk1xnege = clk1xnege;
 end

always@(posedge clk or negedge rst)
 begin
  if(!rst)
   coutpose = 0;
  else if(coutpose == div2)
   coutpose = 0;
  else
   coutpose = coutpose + 1;
 end

always@(negedge clk or negedge rst)
 begin
  if(!rst)
   coutnege = 0;
  else if(coutnege == div2)
   coutnege = 0;
  else
   coutnege = coutnege + 1;
 end

endmodule