我写的比较简单的testbench ,在6.0下可以使用,在6.5下需要用force语句。
`timescale 1ns / 1ns
module test_dso_top() ;
reg pll0_clk ;
reg pll1_clk ;
reg clr ;
reg arm_ncs,arm_noe,arm_nwe;
reg [6:0] arm_addr ;
reg [15:0] data_i ;
wire wrend ;
wire [15:0]arm_data_in ;
reg [15:0]arm_data_out ;
parameter delay = 3 ;
wire enable ;
assign enable = !arm_ncs && !arm_nwe ;
assign arm_data = enable ? arm_data_out : 16'bzzzz_zzzz_zzzz_zzzz ;
assign arm_data_in = arm_data ;
reg clk ;
reg rst ;
always #3 clk = #delay !clk ;
dso_top dso_top_inst (
.pll0_clk(pll0_clk), .pll1_clk(pll1_clk) ,
.clr(clr) ,.data_i(data_i) ,.arm_addr(arm_addr) ,
.arm_ncs(arm_ncs),.arm_noe(arm_noe),.arm_nwe(arm_nwe),
.wrend(wrend) ,.arm_data(arm_data)
) ;
always #5 pll0_clk = ~pll0_clk ;
always #5 pll1_clk = ~pll1_clk ;
initial
begin
pll0_clk = 1'b0 ;
pll1_clk = 1'b0 ;
clr = 1'b0 ;
clk = 1'b0 ;
rst = 1'b0 ;
#5 ;
rst = 1'b1 ;
#5 ;
rst = 1'b0 ;
arm_ncs = 1'b1 ;
arm_noe = 1'b1 ;
arm_nwe = 1'b1 ;
#5 clr = 1'b1 ;
#50 clr = 1'b0 ;
#5 ;
arm_cs(1'b0 , 7'b0101101);
arm_wr(16'b0000_0000_0000_0010) ;
time_delay(5) ;
arm_wr(16'b0000_0000_0000_0000) ;
arm_cs(1'b0 , 7'b0101110);
arm_wr(16'b0000_0000_0000_0001) ;
arm_cs(1'b0 , 7'b0101111);
arm_wr(16'b0000_0000_0000_0001) ;
arm_wr(16'b0000_0000_0000_0000) ;
arm_cs(1'b1 , 7'b0101101);
@(posedge wrend) ;
time_delay(5) ;
arm_cs(1'b0 , 7'b101_0000);
arm_rd ;
arm_cs(1'b0 , 7'b101_0001);
arm_rd ;
time_delay(5) ;
#100 $stop ;
end
always @(posedge clk or posedge rst)
begin
if (rst)
data_i <= 16'b0000_0000_0000_0000 ;
else
begin
data_i[3:0] <= data_i[3:0] + 1'b1 ;
data_i[7:4] <= data_i[7:4] + 1'b1 ;
data_i[11:8] <= data_i[11:8] + 1'b1 ;
data_i[15:12] <= data_i[15:12] + 1'b1 ;
end
end
task time_delay ;
input [7:0]number ;
integer i ;
begin
for( i = 0 ; i <= number ; i = i + 1'b1)
@(posedge pll0_clk) ;
end
endtask
task arm_wr ;
input [15:0]data_reg ;
begin
arm_nwe = 1'b1 ;
arm_data_out = data_reg ;
time_delay(8'h01) ;
arm_nwe = 1'b0 ;
time_delay(8'h03) ;
arm_nwe = 1'b1 ;
time_delay(8'h01) ;
end
endtask
task arm_rd ;
reg [15:0]state_reg ;
begin
time_delay(8'h01) ;
arm_noe = 1'b1 ;
state_reg = arm_data_in;
time_delay(8'h01) ;
arm_noe = 1'b0 ;
time_delay(8'h02) ;
arm_noe = 1'b1 ;
time_delay(8'h01);
end
endtask
task arm_cs ;
input ncs ;
input [6:0]addr ;
begin
arm_ncs = ncs ;
arm_addr = addr ;
time_delay(8'h02);
end
endtask
endmodule