Include below as:
1. Simulation Environment
A SVN Verison Record
A1 DUV SVN PATH+VERSION
A2 TestBench SVN PATH+VERSION
A3 VPLAN(V Request) SVN PATH+VERSION
B EDA TOOLS
B1 Simulator Ver.
B2 UVM Ver.
B3 Wave Viewer Ver.
B4 Coverage Analysis Ver.
2. Testcase summary
2.1 case list
2.2 seed
2.3 case excuation(script)
2.4 case description
2.5 time consuming
3. detail report
3.1 running log analysis
3.2 assertion log analysis
3.3 code coverage log analysis
3.4 function coverage log analysis
3.5 wave analysis (option)
4. Bug statistics
5. Other (something like some important discussion result)