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From ieee 1800

bind_directive ::= 
bind  bind_target_scope [ :  bind_target_instance_list] bind_instantiation  ;  
| bind  bind_target_instance bind_instantiation  ;  

bind_target_scope ::=  module_identifier  | interface_identifier 
bind_target_instance ::=  hierarchical_identifier constant_bit_select 
bind_target_instance_list ::=  bind_target_instance {  ,  bind_target_instance } 
bind_instantiation ::=   program_instantiation  | module_instantiation  | interface_instantiation | checker_instantiation

The  bind  directive can be specified in any of the following:
— A module 
— An interface 
— A compilation-unit scope 
There are two forms of bind syntax. In the first form, bind_target_scope specifies a target scope into which
the bind_instantiation should be inserted. A bind target scope shall be a module or an interface. A bind
target instance shall be an instance of a module or an interface. In the absence of a bind_target_instance_list,
the  bind_instantiation  is  inserted  into  all  instances  of  the  specified  target  scope,  designwide.  If  a
bind_target_instance_list is present, the bind_instantiation is only inserted into the specified instances of
the target scope. The bind_instantiation is effectively a complete module, interface, program, or checker
instantiation statement. 

The second form. of bind syntax can be used to specify a single instance into which the bind_instantiation
should be inserted. If the second form. of bind syntax is used and the bind_target_instance identifier resolves
to both an instance name and a module name, binding shall only occur to the specified instance.


imicman的个人空间 引用 删除 imicman   /   2016-08-10 22:40:17
Example of binding a program instance to a module:

bind cpu fpu_props fpu_rules_1(a,b,c);

— cpu  is the name of the target module.
— fpu_props  is the name of the program to be instantiated.
— fpu_rules_1  is the program instance name to be created in the target scope.
— An instance named  fpu_rules_1  is instantiated in every instance of module  cpu .
— The first three ports of program  fpu_props  get bound to objects  a ,  b , and  c  in module  cpu  (these
objects are viewed from module  cpu ’s point of view, and they are completely distinct from any
objects named  a ,  b , and  c  that are visible in the scope that contains the  bind  directive).

Example of binding a program instance to a specific instance of a module:

bind cpu: cpu1 fpu_props fpu_rules_1(a, b, c);

In the example above, the  fpu_rules_1  instance is bound into the  cpu1  instance of module  cpu .

Example of binding a program instance to multiple instances of a module:

bind cpu: cpu1, cpu2, cpu3 fpu_props fpu_rules_1(a, b, c);

In the example above, the  fpu_rules_1  instance is bound into instances  cpu1 ,  cpu2 , and  cpu3  of module
cpu .
By binding a program to a module or an instance, the program becomes part of the bound object. The names
of  assertion-related  declarations  can  be  referenced  using  the  SystemVerilog  hierarchical  naming

The  bind_instantiation  portion  of  the  bind   statement  allows  the  complete  range  of  SystemVerilog
instantiation  syntax.  In  other  words,  both  parameter  and  port  associations  may  appear  in  the
bind_instantiation.  All  actual  ports  and  parameters  in  the  bind_instantiation  refer  to  objects  from  the
viewpoint of the bind_target_instance.

When an instance is bound into a target scope, the effect will be as if the instance was present at the very end
of the target scope. In other words, all declarations present in the target scope or imported into the target
scope are visible to the bound instance. Wildcard import candidates that have been imported into the scope
are visible, but a bind statement cannot cause the import of a wildcard candidate. Declarations present or
imported into  $unit  are not visible in the bind statement.

The following is an example of a module containing a  bind  statement with complex instantiation syntax.
All identifiers in the  bind  instantiation are referenced from the bind target’s point of view in the overall
design hierarchy.
bind targetmod
mycheck #(.param1(const4), .param2(8’h44))   i_mycheck(.*, .p1(f1({v1, 1’b0, b1.c}, v2 & v3)), .p2(top.v4));




:loveliness: :handshake :victory: :funk: :time: :kiss: :call: :hug: :lol :'( :Q :L ;P :$ :P :o :@ :D :( :)


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