compilation and elaboration

上一篇 / 下一篇  2016-06-23 21:36:28 / 个人分类:验证杂谈


Compilation is the process of reading in SystemVerilog source code, decrypting encrypted code,and analyzing the source code for syntax and semantic errors. 

Elaboration is the process of binding together the components that make up a design. These components can include module instances,program instances,interface instances,checker instances,primitive instances,and the top
level of the design hierarchy. Elaboration occurs after parsing the source code and before simulation; and it involves expanding instantiations,computing parameter values,resoving hierarchical names,establishiing net connectivity and in general preparing the design for simulation.

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