日志
back-slash
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In Verilog, the ‘define macro text can include a backslash ( \ ) at the end of a line to show continuation on
the next line.
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A string literal shall be contained in a single line unless the new line is immediately preceded by a \ (back-
slash). In this case, the backslash and the new line are ignored. There is no predefined limit to the length of a
string literal.
Example 1:
$display("Humpty Dumpty sat on a wall. \
Humpty Dumpty had a great fall.");
prints
Humpty Dumpty sat on a wall. Humpty Dumpty had a great fall.
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If more than one line is necessary to specify the text, the newline shall be preceded by a backslash ( \ )
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注意：反斜杠后面一定不能有任何字符，也就是反斜杠是最后一个字符
在linux服务器上，如果文件采用windos的ODOA换行，需要将文件转化为unix/linux格式，即0D0A->0A
不然，上述两种情况都会编译报错
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