日志
SVTB-top
| |
`timescale 1ns/1ps
module top;
parameter CYCLE = 100;
bit clk;
router_io top_io(clk);
test t();
router dut(
.clk(top_io.clk),
.rstn(top_io.reset_n),
...
);
initial begin
clk =0;
#(`ST) $finish();
end
always #(CYCLE/2) clk = ~clk;
`ifdef WAVEON
initial begin
$fsdbDumpfile("my_wave");
$fsdbDumpvars(0,"+all");
end
`endif
endmodule
/1 
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