#########################################
# Clock define command and parameters
########################################
(1) create_clock

(2) create_generated_clock
NAME
       create_generated_clock
              Creates a generated clock object.

SYNTAX
       string create_generated_clock
              [-name clock_name]
              -source master_pin
              [-divide_by divide_factor | -multiply_by multiply_factor |
               -edges edge_list ]
              [-combinational]
              [-duty_cycle percent]
              [-invert]
              [-edge_shift edge_shift_list]
              [-add]
              [-master_clock clock]
              [-pll_output output_pin]
              [-pll_feedback feedback_pin]
              [-comment comment_string]
              source_objects
EXAMPLE
pt_shell> create_generated_clock -edges {1 1 3} -edge_shift {0 5 0} \
                   -invert -source [get_pins CLK] [get_pins pinf2]
pt_shell> create_generated_clock -edges {1 1 2 2 3} -edge_shift {0 2.5 0 2.5 0} \
                   -source [get_pins CLK] [get_pins pinf2]

(3)set_clock_latency 2.2 [get_clocks BZCLK]
# Both rise and fall latency is 2.2ns.
# Use options -rise and -fall if different.

(4)set_clock_uncertainty 0.250 -setup [get_clocks BZCLK]
set_clock_uncertainty 0.100 -hold [get_clocks BZCLK]

#################################################
# Input and output
#################################################
(1) set_input_delay 200 [get_port XXX] -max -clock [get_clocks clock_name]
NAME
       set_input_delay
              Defines the arrival time relative to a clock.

SYNTAX
       string set_input_delay
              [-clock clock_name]
              [-reference_pin pin_port_name]
              [-clock_fall]
              [-level_sensitive]
              [-rise]
              [-fall]
              [-max]
              [-min]
              [-add_delay]
              [-network_latency_included]
              [-source_latency_included]
              delay_value
              port_pin_list
(2) set_output_delay

#################################################
# Data constraints
#################################################
(4) set_case_analysis
set_case_analysis 1 [get_pins XXX]

(5) set_disable_timing
set_disable_timing -form. B to Y [get_cells XXXX]

(6) set_sense
NAME
       set_sense
              Specifies unateness propagating forward for pins with respect to
              clock source.

SYNTAX
       string set_sense
              [-type clock | data]
              [-positive]
              [-negative]
              [-stop_propagation]
              [-pulse pulse_type ]
              [-clocks clock_list]
              object_list
EXAMPLE:
set_sense -type clock -stop_propagation -clock [all_clocks] [get_pins XXXX]

(7) set_false_path
NAME
       set_false_path
              Identifies  paths in a design that are to be marked as false, so
              that they are not considered during timing analysis.

SYNTAX
       Boolean set_false_path
              [-setup]
              [-hold]
              [-rise]
              [-fall]
              [-reset_path]
              [-from from_list
                 | -rise_from rise_from_list
                 | -fall_from fall_from_list]
              [-through through_list]
              [-rise_through rise_through_list]
              [-fall_through fall_through_list]
              [-to to_list
                 | -rise_to rise_to_list
                 | -fall_to fall_to_list]
              [-comment comment_string]
EXAPMLE
pt_shell> set_false_path -rise_from U14/Z -to ff29/Reset
set_false_path -from [get_clocks USBCLK] \
-to [get_clocks MEMCLK]
# This specification is explained in more detail in Chapter 8.

(8) set_disable_timing -from A -to Y [get_cells cell_path]
NAME
       set_disable_timing
              Disables timing arcs in a circuit.

SYNTAX
       string set_disable_timing
              [-from from_pin_name -to to_pin_name]
              object_list


(8) set_multicycle_path
NAME
       set_multicycle_path
              Defines the multicycle path.

SYNTAX
       Boolean set_multicycle_path
              [-setup]
              [-hold]
              [-rise]
              [-fall]
              [-start]
              [-end]
              [-reset_path]
              [-from from_list
                 | -rise_from rise_from_list
                 | -fall_from fall_from_list]
              [-through through_list]
              [-rise_through rise_through_list]
              [-fall_through fall_through_list]
              [-to to_list
                 | -rise_to rise_to_list
                 | -fall_to fall_to_list]
              [-comment comment_string]
              path_multiplier

EXAMPLE
pt_shell> set_multicycle_path 2 -from ff1/CP -through {U1/Z U2/Z} -through {U3/Z U4/C} -to ff2/D
pt_shell> set_multicycle_path 3 -start -from { clk50mhz } -to { clk10mhz }

set_operating_conditions “WCCOM” -library mychip
# Use the operating condition called WCCOM defined in the
# cell library mychip.


set_data_check  -setup value -from from_path -to to_path

remove_data_check -from from_path -to to_path