[b]Perform. Timing-Driven Packing and Placement [/b](Advanced) (Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3, Spartan-3A and Spartan-3E devices only)
Specifies whether or not to give priority to timing critical paths during packing in the Map process. User-generated timing constraints are used to drive the packing and placement operations. The timing constraints are generally specified in the User Constraints File (UCF) and are annotated onto the design during the Translate process. At the completion of the process, the result is a completely placed design, and the design is ready for routing. If Timing-Driven Packing and Placement is selected in the absence of user timing constraints, the tools will automatically generate and dynamically adjust timing constraints for all internal clocks. This feature is referred to as Performance Evaluation mode. This mode allows the clock performance for all clocks in the design to be evaluated in one pass. The performance achieved by this mode is not necessarily the best possible performance each clock can achieve. Instead it is a balance of performance between all clocks in the design. By default, this property is set to False (checkbox is blank).
[color=Red]大家都知道,略[/color]
[b]Perform. Timing-Driven Packing[/b] (Advanced) (Virtex and Spartan-II devices only)
Specifies whether or not to give priority to timing critical paths during packing in the Map process. User-generated timing constraints are used to drive the packing operation. The timing constraints are generally specified in the User Constraints File (UCF) and are annotated onto the design during the Translate operation. By default, this property is set to False (checkbox is blank), and timing-driven packing is not performed.
[color=Red]大家都知道,略[/color] [b] Map Effort Level (Advanced)[/b] (Virtex-II and Virtex-II Pro, Virtex-4, Spartan-3, Spartan-3A and Spartan-3E devices only)
Note Available only when Perform. Timing-Driven Packing and Placement is set to True (checkbox is checked). Specifies the effort level you want to apply to the Map process. [color=Red]The effort level controls the amount of time used for packing and placement by selecting a more or less CPU-intensive algorithm for placement.[/color] You can set the effort level from Standard (fastest run time) to High (best results). This property is available only when the Perform. Timing-Driven Packing and Placement property in this dialog box is set True (checkbox is checked). Select an option from the drop-down list. - Standard: Gives the fastest run time with the lowest mapping effort. Appropriate for a less complex design. - Medium: Gives a medium run time with good mapping results. - High: Gives the longest run time with the best mapping results. Appropriate for a more complex design. By default, this property is set to Medium.
[color=Red]大家都知道,略[/color]
[b]Extra Effort (Advanced)[/b]
Map spends additional run time in an effort to meet difficult timing constraints. Note The Extra Effort property is available only when the Map Effort Level is set to High. Select an option from the drop-down list. - None: No extra effort level is applied. - Normal: Runs until timing constraints are met unless they are found to be impossible to meet. This option focuses on meeting timing constraints. - Continue on Impossible: Continues working to improve timing until no more progress is made, even if timing constraints are impossible. This option focuses on getting close to meeting timing constraints. By default, this property is set to None.
Specifies the effort level you want to apply to the Map process. The effort level controls the amount of time used for packing and placement by selecting a more or less CPU-intensive algorithm for placement. You can set the effort level from Standard (fastest run time) to High (best results). Select an option from the drop-down list. - Standard: Gives the fastest run time with the lowest mapping effort. Appropriate for a less complex design. - High: Gives the longest run time with the best mapping results. Appropriate for a more complex design. By default, this property is set to High.
[color=Red]大家都知道,略[/color]
[b]Placer Extra Effort (Advanced) (Virtex-5 only)[/b]
This property sets the extra effort level for timing-driven packing. This property is only enabled if the Placer Effort Level is set to High. Select an option from the drop-down list. - None: No extra effort level is applied. - Normal: Runs until timing constraints are met unless they are found to be impossible to meet. This option focuses on meeting timing constraints. - Continue on Impossible: Continues working to improve timing until no more progress is made, even if timing constraints are impossible. This option focuses on getting close to meeting timing constraints. By default, this property is set to None.
Specifies a mapping initialization value with which to begin the map attempts. Each subsequent attempt is assigned an incremental value based on the mapping initialization value. By default, this property is set to 1. This property is available only when the Perform. Timing-Driven Packing and Placement property in this dialog box is set to True (checkbox is checked).
Specifies whether or not to run a process that revisits the combinatorial logic within a design to see if any improvements can be made that will improve the overall quality of results. Timing constraints and logic packing information are considered when this process is run. This property is part of the physical synthesis tools in ISE. By default, this property is set to False (checkbox is blank), and this process is not run on the design. This property is available only when the Perform. Timing-Driven Packing and Placement property in this dialog box is set to True (checkbox is checked).
[b]Register Duplication[/b] (Advanced) (Not available for Virtex or Spartan-II devices)
Specifies whether or not you want to replicate the registers to help control fanout. By default, this property is set to False (checkbox is blank), and register duplication is not performed during timing optimization and fanout control. This property is available only when the Perform. Timing-Driven Packing and Placement property in this dialog box is set True (checkbox is checked).
[color=Red]寄存器复制用于减小扇出,以满足时序约束。[/color]
[b]Global Optimization[/b] (Advanced) (Virtex-4 and Virtex-5 only)
When this property is set to True (checkbox is checked), Map performs global optimization routines on the fully assembled netlist before mapping the design. Global optimization includes logic remapping and trimming, logic and register replication and optimization, and logic replacement of tristates. These routines will extend the runtime of Map because extra processing occurs. By default, this property is set to False (checkbox is blank). With Global Optimization set to True, using Partitions is not recommended, and Formal Verification flows will be negatively affected. Also, certain Map properties are not allowed in conjunction with Global Optimization: neither Trim Unconnected Signals (-u) nor Replicate Logic to Allow Logic Level Reduction (-l) may be set to False when running Global Optimization.
[b]Retiming[/b] (Advanced) (Virtex-4 and Virtex-5 only)
When this property is set to True (checkbox is checked), registers are moved forward or backwards through the logic to balance out the delays in a timing path to increase the overall clock frequency. The overall number of registers may be altered due to the processing. By default, this property is set to False (checkbox is blank). This property is available only when the Global Optimization property is set to True (checkbox is checked).
[b]Equivalent Register Removal [/b](Advanced) (Virtex-4 and Virtex-5 only)
When this property is set to True (checkbox is checked), any registers with redundant functionality are examined to see if their removal will increase clock frequencies. By default, this property is set to True (checkbox is checked). This property is available only when the Global Optimization property is set to True (checkbox is checked).
This property controls the use of timing constraints during placement. The primary method of specifying timing requirements is by entering them in the User Constraints File (UCF). For detailed information about timing constraints, see the Constraints Guide. If this property is not selected (checkbox is blank), Map packs and places in accordance with any timing constraints specified in the User Constraints File (UCF). If this property is selected (checkbox is checked), timing constraints in the UCF are ignored when Map runs. Map will proceed as follows: For all devices except Virtex-5, packing and placement will run without timing constraints. The Timing Mode property below will indicate Non Timing Driven mode. For Virtex-5, the setting of the Timing Mode property (described below) determines whether MAP will automatically generate timing constraints to control packing and placement or will run without timing constraints.
This property is enabled when the Ignore User Timing Constraints property (see above) is selected. Select an option from the drop-down list. - Performance Evaluation (Virtex-5 Only): This selection triggers the "Performance Evaluation" mode. In this mode timing constraints specified in the User Constraints File (UCF) are ignored. Instead, timing constraints for all internal clocks are generated automatically and dynamically adjusted during Map to increase performance. This mode is used to evaluate realistic performance targets for the design. Performance Evaluation is described in the "MAP" chapter in the Development System Reference Guide. - Non Timing Driven: In this mode, timing constraints specified in the UCF are ignored, and packing and placement will run with no timing constraints. This selections will make the Map process run faster, but will not take into account timing constraints while generating the resulting output.
Specifies whether or not to trim unconnected components and nets from the design before mapping occurs. Leaving this option blank is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, set this property to False (checkbox is blank) to map unconnected components and nets. By default, this property is set to True (checkbox is checked), and unconnected components and nets are trimmed.
[b]Replicate Logic to Allow Logic Level Reduction[/b] (Advanced)
Specifies whether or not to replicate logic, such that a single driver that drives multiple loads is replicated, and each separate component drives an individual load. This option is useful for creating a mapping strategy that may more readily meet your timing constraints. It reduces the number of logic elements through which a signal must pass, thereby eliminating path delays. By default, this property is set to True (checkbox is checked), and logic is replicated.
[b]Allow Logic Optimization Across Hierarchy[/b] (Advanced)
When this property is set to True (checkbox is checked), Map ignores any Keep Hierarchy properties set for the Synthesize process and Map can perform. optimizations across any hierarchical boundaries. This property is used to preserve the signals that span the hierarchical boundaries for the purpose of simulation, or to ensure that optimizations do not affect of the behavior. of the designs using Partitions. Better timing performance can be attained by performing such optimizations. By default, this property is set to False (checkbox is blank).
Specifies the maximum size of functions covered for FPGA architectures. Select a function between 4 (F4MUX) and 8 (F8MUX) from the drop-down list. By default, this option is set to 6 for Virtex-5 devices, and 4 for all other devices.
Specifies the criteria used during the "cover" phase of MAP. In the "cover" phase, MAP assigns the logic to CLB function generators (LUTs). Select an option from the drop-down list. - Area: Select Area to make reducing the number of LUTs (and therefore the number of CLBs) the highest priority. - Speed: Select Speed to make reducing the number of levels of LUTS (the number of LUTs a path passes through) the highest priority. This setting makes it easiest to achieve your timing constraints after the design is placed and routed. For most designs there is a small increase in the number of LUTs (compared to the area setting), and in some cases the increase may be large. - Balanced: Select Balanced to balance two priorities; reducing the number of LUTs and reducing the number of levels of LUTs. The Balanced option produces results similar to the Speed setting but avoids the possibility of a large increase in the number of LUTs. - Off: Select Off to disable optimization. By default, this property is set to Area.
Specifies whether or not to display a detailed report. A detailed Map Report displays redundant blocks that were removed and signals that were merged during the mapping process. It also displays expanded logic, signal cross-references, and symbol cross-references. By default, this property is set to False (checkbox is blank), and a detailed Map Report is not generated.
[color=Red]产生详细MAP报告:默认关闭该选项,看需要自己决定吧。[/color]
[b]Use RLOC Constraints[/b] (Advanced)
Specifies whether or not to use the RLOC information that contains the relative placement of one CLB to another. By default, this property is set to True (checkbox is checked), and MAP uses the RLOC information, even invalid information that could result in a Map process error.
Controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. Select an option from the drop-down list. - Off: Select Off to pack flip-flops or latches as specified by your design entry method. - For Inputs Only: Select Inputs Only to pack flip-flops or latches into input I/O cells. - For Outputs Only: Select Outputs Only to pack flip-flops or latches into output I/O cells. - For Inputs and Outputs: Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells. By default, this property is set to Off for Virtex-5 devices, and For Inputs and Outputs for all other devices.
Controls register ordering. When you map a design containing registers, the mapper can optimize the way the registers are grouped into CLBs. This optimized mapping is called register ordering. By default, this property is set to Off (checkbox is blank).
When set to True (checkbox is checked), this option instructs Map to pack the design logic as densely as possible. This is done at the risk of negative place and route performance. By default, this property is set to False (checkbox is blank).
Specifies how densely logic will be partitioned using a percentage value. A higher percentage number will result in lower density packing. A high CLB pack factor percentage can adversely affect place and route performance, resulting in higher delays and more unrouted nets. Note This property is not available for Virtex-5 devices. The command line equivalent to setting this property is -c [packfactor], where packfactor is the percentage of CLBs available in a target device for packing your designs logic. Enter a numeric value in this property. By default, this property is set to 100 (%) which means that all CLBs in a target part are available for design logic. This property is grayed out and cannot be set when either the Perform. Timing-Driven Packing and Placement property is set True (checkbox is checked) or the Perform. Timing-Driven Packing property is set True (checkbox is checked).
Specifies the type of bus transformation that Map will perform. Note This property is not available for Virtex-5, Virtex-4, Spartan-3, or Spartan-3E devices because tri-state buffer transformations are performed automatically for these devices. Select one of the options from the drop-down list. -Off: Does not transform. tristate buses. - On: Transforms tristate buses to LUT or CY logic, as necessary. - Aggressive: Transforms all tristate buses to LUT or CY logic. - Limit: Transforms only the portions of buses that exceed the device limitations. By default, this property is set to Off.
LUT combining enables the merging of LUT pairs with common inputs into single dual-output 6-input LUTs in order to improve design area. This optimization process may reduce design speed. Select one of the options from the drop-down list. - No: Disables LUT combining. - Auto: Map tries to make a tradeoff between area and speed. - Area: Map performs maximum LUT combining to provide as small an implementation as possible. By default, this property is set to Off.
[b]Power Reduction[/b] (Advanced) (Spartan-3, Spartan-3A, Spartan-3E, and Virtex-4 only)
If enabled, Map will optimize placement during timing-driven packing and placement to reduce the power consumed by the design. This property is enabled when the Perform. Timing-Driven Packing and Placement property is set enabled (checkbox is checked). By default, this property is disabled.
[color=Red]功率削减,这个选项可以帮助设计降低功耗。[/color] [color=Red]前提:Perform. Timing-Driven Packing and Placement[/color]
[b]Power Activity File[/b] (Advanced) (Spartan-3, Spartan-3A, Spartan-3E, and Virtex-4 only)
This property allows you to specify a simulation file, *.vcd or *.saif, to guide Map when it optimizes the design for power reduction. This file is the output of a simulation run on the design. For power reduction, Map uses this file to set frequencies and activity rates of internal signals, which are signals that are not inputs or outputs but internal to the design. Note Simulation is the most accurate method of determining the exact activity rates. Back-annotated post-place and route simulation provides the best data for determining activity rates since it most closely represents physical implementation. By default, this property is blank (no file name).
Enter additional command line options. Multiple options are separated with a space. The options entered in this property appear first on the command line, before all other property options specified in the graphical user interface. Avoid setting duplicate property options. For more information about command line options, see the Development System Reference Guide.