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uvm: tlm 1.0

已有 1172 次阅读| 2018-8-28 23:28 |个人分类:UVM|系统分类:芯片设计

driver, monitor等不太需要,但实现复杂的scoreboard和coverage collector,需要用到UVM tlm1.0 或2.0的功能,但tlm 1.0简单实用,比较流行。
1. push
         Producer: uvm_blocking_put_port.put()
         Consumer:
                      class consumer extends uvm_component;
                         uvm_blocking_put_imp#(packet, consumer) put_export;
                         function void build_phase(uvm_phase phase);
                             ...
                             put_export = new("put_export", this);
                         endfunction: build_phase

                         virtual task put(packet(packet tr);
                               //process tr
                          endtask: put
                      endclass
                       

2. get
          Producer:
            class producer extends uvm_component;
                 uvm_blocking_get_imp#(packet, producer) get_export;
                 function new(string name, uvm_component parent);
                      super.new(name, parent);
                      ...
                      get_export = new("get_export");
                 endfunction
                  //implement "get()"
                  virtual task get(packet tr); ... endtask: get
              endclass
          Consumer:
              class consumer extends uvm_component;
                   uvm_blocking_get_port get_port;
                   function new(string name, uvm_component parent);
                      super.new(name, parent);
                      ...
                      get_port = new("get_port");
                 endfunction
               
                  virtual task main_phase(uvm_phase phase);
                     ...
                     get_port.get(tr);
                     ...
                  endtask: main_phase

             Env connection:
                  class env extends uvm_env;
                      ...
                     producer p;  consumer c;
                     virtual function void connect_phase(uvm_phase phase);
                          c.get_port.connect(p.get_export);
                      endfunction: connect_phase
                      ...
                   endclass
              endclass
3. fifo
         class env extends uvm_env;
             ...
             uvm_tlm_fifo #(packet) tr_fifo
              ...
              virtual function void build_phase(uvm_phase phase);
                 p = producer::type_id::create("p", this);
                 c = consumer::type_id::create("c", this);
                 tr_fifo = new("tr_fifo", this);
              endfunction: build_phase

              virtual function void connect_phase(uvm_phase phase);
                  p.put_port.connect(tr_fifo.put_export);
                  c.get_port.connect(tr_fifo.get_export);
               endfunction: connect_phase
               ...
            endclass

4. uvm_analysis (broadcast)
          uvm_analysis_port:      producer call "write()"
          uvm_analysis_imp:       receiver implement "write()"
          uvm_analysis_export:   receiver: hierarchical "port_through", used to connect

          如果component需要2个或2个以上的imp:
         `uvm_analysis_imp_decl(_before)
         `uvm_analysis_imp_decl(_after)
         ...
         //implement write function
         virtual function void write_before(before b_tr)
         virtual function void write_after (after a_tr)
         `uvm_analysis_imp_before #(before, packet) before_export;
         `uvm_analysis_imp_after #(after, packet) after_export
         

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