The commonly adopted low-power design strategies and their application are explained briefly in this section.
- Clock Gating
Clock gating is a dynamic power reduction method in which the clock signals are stopped for selected register banks during times when the stored logic values are not changing. It is a well-established power-saving technique that has been used for years.
- Leakage Power Reduction with Multi-Vth Optimization
A multi-Vth (or multi-threshold library) offers two or more different cells to implement each logic function, each using a different transistor threshold voltage. A low-Vth cell has higher speed, but higher sub-threshold leakage current. A high-Vth cell has low leakage current, but less speed. During optimization, the implementation tool can choose the appropriate type of cell to use based on the tradeoff between speed and power. For example, the tool can use low-Vth cells in the timing-critical paths for speed and high-Vth cells everywhere else for lower leakage power.
- Multivoltage Designing
A multivoltage design consists of distinct design partitions which operate at different voltage levels. Design partitions with lower speed are operated at lower supply voltages, to reduce dynamic power consumption.
- Power Gating
In power gated designs, portions of the chip are shut down completely during periods of inactivity. This strategy reduces overall power consumption substantially because both leakage power and switching power are almost insignificant in shutdown sate.
- Dynamic Voltage and Frequency Scaling
Dynamic voltage scaling allows voltage-level variations during chip operation to meet the dynamic performance needs of the system. To save additional dynamic power, frequency can also be scaled in one or more of these power modes. This combination of scaling techniques is referred to as Dynamic Voltage and Frequency Scaling (DVFS).