By Yushan Li, National Semiconductor - July 18, 2008

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The performance of a switching regulator for the given external passive components is largely determined by how well the closed loop is being compensated. An excellent loop-compensation design is essential to high performance switchers. It is also often the most difficult block to design, partly due to the switching activity. In the compensation design, we often linearize the loop to simulate the feedback stability using the average switching model (Appendix B.2.2 of Reference 1). However, you can simulate the phase margin and gain margin directly from the switching feedback loop. This is achieved through the PSS (periodic steady-state) and PAC (periodic small-signal AC) analyses. PSS and PAC are often used for RF simulations, where the carrier is a periodic signal. PSS and PAC analyses are available in commercial simulators such as Cadence SpectreRF (Reference 2).

PSS analysis uses the shooting method to find the periodic-steady-state solution. The shooting method solves a boundary value problem by reducing it to the solution of an initial value problem. PAC analysis is used to compute transfer functions for circuits that exhibit frequency translation. It is a small signal analysis like AC analysis, except the circuit is first linearized about a periodically varying operating point as opposed to a simple DC operating point. A PAC analysis cannot be used alone; it must follow a PSS analysis.

In PWM switching regulators, the switching frequency is constant, so the steady state is periodic as well. PSS analysis can be used to find the periodic-steady-state solution. PAC analysis can be used to compute the loop gain, phase margin, crossover frequency, and gain margin. In , a simple voltage mode buck switcher is constructed, which has blocks including switches (M0/D0), the output filter components (L0/C0), the load (R0), the feedback resistor divider (R1/R2/R3), the error amplifier (Iea) and associated compensation network (R1/R2/C1/R4/C2), and the PWM comparator (Ipwm_comp) fed by the sawtooth ramp (V2). The equivalent averaging switching model is also constructed for the small signal AC analysis, in the bottom schematics of . It has new blocks: switch_ model to model the switches and E2/Ilimiter to linearize the PWM comparator gain and limit the duty cycle within 0 to 100%. Readers can exercise and verify the results using the detailed netlists for the simulations [Link to zip file].

In this example, the input voltage is 3.6V, and the output is designed to regulate to 1.5V for assumed 6Ω load, with 0.5V reference. The inductance is 10 μH, the capacitance is 10 μF, and the switching frequency is 1 MHz. The switcher has two complex poles introduced by the output filter with its resonance frequency around 15.9 kHz (1/(2π*√(L*C))). It is easy to show that the compensation network transfer function is:

H(s) = (1+ s*R2*C1) * (1 + s*R4*C2) / (s*(R1+R2)*C2 * (1 + s*R1//R2*C2))

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The compensation introduces two real zeroes (in left half plane) located at: z1 = 1/ (2π*R2*C1), and z2 = 1/(2π*R4*C2) to cancel the output complex poles. The compensation also has the integrator with its pole at 0, and a high frequency pole located at 1/ (2 π *R1//R2*C1) to roll off the gain above the crossover frequency to filter out the high-frequency switching noise. The crossover frequency or unit-gain bandwidth is roughly located at 1/ (2π*(R1+R2)*C2).

To simulate the open-loop gain, a small signal voltage injection is performed at the feedback node Vfb, as the feedback network impedance is much larger than its load, so the loading effect of the loop is negligible in this case. As the AC or PAC analyses sweep the frequency, the loop gain can be calculated from the small signal gain ∂Vout/∂Vfb for each swept frequency. From the open loop gain, the crossover frequency, phase margin, and gain margin can be obtained.

 shows the simulated waveforms from the PSS/PAC and transient analyses with the switcher, and the AC analysis from the equivalent averaging switching model. From the waveforms, we can clearly see the consistence of the loop-gain simulations between PAC (top left) and AC (bottom left) analyses. As a matter of fact, they are exactly the same when overlapped, except in the frequency near its switching frequency (1 MHz). This is to be expected because the averaging switching model removed the switching effect. The crossover frequency and phase margin are 76 kHz and 54o, respectively. The voltage waveforms of a few nodes are also compared between the PSS and transient waveforms, and they are also consistent. PSS can also show the fundamental and higher-order harmonics in the spectrum point of view.

In summary, a simple voltage-mode buck switcher is demonstrated with the PID compensation. PSS/PAC analyses are performed for the switcher, and the loop gain is calculated from the PAC analysis without its equivalent small-signal linear circuitry. The small-signal linear circuit is also constructed with the averaging switching model to verify the loop gain from the PAC analysis. The loop-gain waveforms from the PAC and AC analyses show exact consistency, except near the switching frequency, as the averaging switching circuit doesn’t model the switching effect.

From this demonstration, we conclude that we can design the compensation network directly from the PSS/PAC analysis of the switcher schematics, instead of constructing its equivalent linear circuit. We can also verify the compensation design based on the PSS/PAC analyses if the compensation has been designed by its equivalent linear model.

The PSS/PAC analyses may also be applied for the switching capacitor or charge-pump regulators. Though it is not shown here, the technique has also been exercised successfully for inductorless switching regulators. The advantage of using PSS/PAC is even more obvious in these cases, as an accurate average mode may not be available. The principle and usage are the same as in the case of magnetic switching regulators. PSS/PAC will be able to directly show the open loop-gain-transfer function, and thus help the designer to optimize the loop compensation.