最近拿到一个foundry 65nm的工艺，但是工艺说明文档上并没有写电容的匹配精度，请问一般在65nm工艺下电容的失配随面积是怎样变化的呢？

这个工艺提供的电容是长条形的，W固定为0.1um，只能改变L和finger

I guess it is so called "vertical parallel plate capacitor."
I suppose it (the vertical plates, the vertical walls) is built by the mutiple via and metal layers of the process technology.
The higher number of interconnect layers (usually associated with more advanced technology nodes), the higher unit capacitance.

Refer to the following URL for discussions overseas.

http://www.designers-guide.org/Forum/YaBB.pl?num=1146378302

The original IEEE JSSC paper is attached for your reference reference.

As a matter of fact foundries do have matching data (and technical documents) about this type of capacitors.
I used such type of capacitor since 2001 (0.18-um node).
I know TSMC and Global Foundry provide mismatch data of such type of capacitors.t
Sorry, I cannot attach their data to this site (legal issue).
Simply ask the customer support engineers of foundries to get these technical reports.

More inputs
The capacitor per unit area is actually a function of the following:
1. Length of metal stripes (L)
2. Spacing of metal stripes on the same layer (S)
3. Width of the metal stripes
4. Number of parallel metal stripes (so called "M", i.e., the number of fingers)
5. Number of metal layers that can be used in the capacitor layout

Area of the capacitor layout ~= L x [(M-1) x S + M x W]

Specifying S in the capacitor layout is not straightforward.  (Not simply to use min. spacing)
Just imagine the the vertical walls are built by stripes of metal and vias.
In between the vias are atually filled by IMD (inter-metal-dielectrics), which is void (in terms of conducting material).
So the conductor (plate) surface is not continuous.
Even more, it can be considered zig-zag.

So specifying S by the minimum DR is probably not the best approach.
Making S >> minimum spacing (e.g., S = 3 x min. metal-to-metal spacing) between metal stripes improves the uniformity, at the cost of reduced capacitance per unit-area.

I guess, there would be a good number of S between min. DR allows and 3 times this number, which give good tradeoff between layout area and capacitor matching perfomance.

Other notes
Avoid using M1 as the starting conducting layer, since M1-to-substrate/bulk parasitic capacitance is relatively a large percentage of the total capacitance.
Use top metal layer to increase the capacitance per unit area.  M_top is thicker and creates more "side-wall" capacitance.  (Since M_top spacing is also a larger number compared to those in lower metal layers.)  If necessary, rotate the M_top stripes by 90 degrees.  Overlay the (rotated) M_top fingers on top of lower-layer layout.
Depending on how high your vertical wall stacks up, keep the neighborhood layout components at least two times the distance from the capacitor, such that the unwanted signal coupling is reduced.  A simple rule of thumbs: # of metal layer = N, the distance you want to keep your non-relevant components away from the edge of the capacitor = 2 N um.  So you see, this capacitor layout is not too area efficient.