As complementary metal oxide semiconductor (CMOS) logic scales down, it needs ultrathin gate oxides and a reduced operating voltage for high performance. At the same time, however, an increasing number of applications require dual voltage or dual gate oxide (DGO) on a chip to interface to a higher external voltage. Moreover, to facilitate merged logic and memory circuits, DGO for memory and logic is also required. In a conventional DGO process using wet etching, a thick oxide layer is formed by reoxidizing the residual oxide after partially etching the pregrown oxide, while a thin oxide layer is grown on a clean silicon surface after thoroughly etching the pregrown oxide. Thus, the thick oxide layer in the DGO process has a tendency to poor reliability compared with a thin oxide layer and single-step-grown oxide with the same thickness.
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Why Triple Oxide?
As
process geometries have shrunk, and transistors became smaller and thus
cheaper, the gate oxide (the layer of silicon-dioxide that separated
the gate from source and drain) had to be made thinner to achieve high
switching speed. But thin oxide (down to 16 Å = 1.6 nm) cannot tolerate a
voltage that is higher than about 1.5 V. (Excessive voltage leads to
degradation over time, especially at elevated temperatures, and we
expect our circuits to stay within specification for at least 20 years).
That is why Vccint has been reduced to 1.2 V for Virtex-4 and to 1.0 for Virtex-5 devices.
Thin
oxide is necessary for high performance, and important for low dynamic
power consumption, but it also causes the leakage current to increase
dramatically. There are two components to the leakage current: gate
leakage current which just passes through the very thin gate oxide, and
source-drain leakage which is caused by transistors being not completely
turned off. The threshold voltage does not scale perfectly with Vcc.
Source-drain
current increases exponentially with temperature, and thus dominates at
high temperature, while gate leakage dominates at room temperature, but
increases only slightly with temperature.
The
I/O transistors must interface with legacy devices that operate on 3.3
V. Here we need thicker gate oxide, to withstand at least 3.6 V,
preferably 4 V. (We managed to convince most customers that 5 V
tolerance is no longer needed.) Most modern CMOS devices thus use two
different gate oxide thicknesses, a thin oxide for the high-performance
core of the chip (memory, microprocessor or FPGA) and a thicker oxide
for the I/O transistors.
Virtex-4
and Virtex-5 go one step further and use a third thickness, called
mid-ox since it is between the two established thicknesses. An FPGA
always has many transistors that reside in the core logic, but they have
no reason to be fast. Most obvious are the millions of transistors that
store the configuration (six transistors for each configuration bit).
Giving these transistors a thicker gate oxide reduces their leakage current substantially.
That is why Xilinx uses “triple-oxide technology”, which we expect to become the standard for the industry.
Peter Alfke
Message Edited by peter.a on
04-21-2008 10:10 AM
peter.a
- edited
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