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Question:

Is there a test bench showing how to add jitter to the PRBS source?

Answer:

The attached example contains a sample and hold Verilog-A model which can be used to add jitter to a PRBS source. Care should be taken so that the jitter clock occurs in middle of PRBS clock rate to avoid sampling on the rising or falling edge.

---------------------------Testbech : jitter.sp ---------------------------

* jitter
.option post

.hdl "sample_hold.va"

.param rate = 1066e6
.param delay  = 1ns
.param slew = 50p

v0 n0 0 pulse (0 1.5 "delay-slew+(1/rate-slew)/2" slew slew "1/rate-slew" "2/rate")
r0 n0 0 1k

vj jitter 0 pulse (0 1.5 "delay-slew+(1/rate-slew)/2" slew slew "1/rate-slew" "2/rate")
+perjitter=50p
rj jitter 0 1k

vp prbs 0 LFSR 0 1.5 delay slew slew rate 1 [5 2]
rp prbs 0 1k

x0 prbs out jitter sample_hold threshold=0.75 risetime='slew'

.tran 1p 100n

.probe v(*)

.end
---------------------------Verilog-A : sample_hold.va ---------------------------

// Sample and hold circuit based on LRM 2.0 example p 6.14

`include "disciplines.vams"
module sample_hold(in,out,clk);
   input in,clk;
   output out;
   voltage in,out,clk;
 
   parameter real risetime = 1.0e9 from (0:inf);
   parameter real threshold = 2.5;
   real v;

   analog begin
       @(cross(V(clk)-threshold,0)) 
           v = V(in);             
       V(out) <+ transition(v,0,risetime);
   end
endmodule
-------------------------------------------------------------

Run command:

 % hspice -i jitter.sp -o jitter

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Question:

How can I generate a pulse waveform. (source) with period and frequency jitter 
that I can use during the functional verification of designs like PLLs and SERDES? 

Answer:

This can be done effectively and efficiently with the Verilog-A code shown below.

//////////////////////////////////////////////////////////////
`include "disciplines.vams"
`include "constants.vams"
module osc (out);
output out; electrical out;
parameter real freq=20e6 from (0:inf);  //output frequency
parameter real Vlo=0, Vhi=1; //output level
parameter real tt=0.01/freq from (0:inf);  //rise time and fall time
parameter real fmJitter=0 from [0:0.1/freq);
parameter real pmJitter=0 from [0:0.1/freq);
integer n, fmSeed, pmSeed;
real next, dT, dt;
analog begin
@(initial_step) begin
fmSeed = 286;
pmSeed = -459;
next = 0.5/freq + $realtime;
end
@(timer(next + dt)) begin
n = !n;
dT = fmJitter*$dist_normal(fmSeed,0,1);
dt = pmJitter*$dist_normal(pmSeed,0,1);
next = next + 0.5/freq + 0.707*dT;
end
V(out) <+ transition(n ? Vhi : Vlo, 0, tt); 

end
 // 
endmodule
//////////////////////////////////////////////

The jitter can have any of the following distributions:

    Distribution                                   verilog A functions
**************************************************************
Uniform. Distribution                                 $dist_uniform.
Normal (Gaussian) Distribution                       $dist_normal
Exponential Distribution                             $dist_exponential
Poisson Distribution                                 $dist_poisson
Chi-Square Distribution                              $dist_chi_square
Erlang Distribution                                  $dist_erlang
****************************************************************
For more information please refer to the Verilog-A LRM.

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