The front-end-of-line (FEOL) is the first portion of IC fabrication where the individual devices (transistors, capacitors, resistors, etc.) are patterned in the semiconductor.[1] FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers.

FEOL contains all processes of CMOS fabrication needed to form. fully isolated CMOS elements:

    * Selecting the type of wafer to be used; Chemical-mechanical planarization and cleaning of the wafe.
    * Shallow trench isolation (STI) (or LOCOS in early processes, with feature size > 0.25 μm) Well formation
    * Gate module formation
    * Source and drain module formation

The back end of line (BEOL) is the second portion of IC fabrication where the individual devices (transistors, capacitors, resistors, etc.) get interconnected with wiring on the wafer.[1] BEOL generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections.

After the last FEOL step, there is a wafer with isolated transistors (without any wires). In BEOL part of fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC process, more than 10 metal layers can be added in the BEOL.

Steps of the BEOL:

    * Silicidation of source and drain regions and the polysilicon region.
    * Adding a dielectric (first, lower layer is Pre-Metal dielectric, PMD - to isolate metal from silicon and polysilicon), CMP processing it
    * Make holes in PMD, make a contacts in them.
    * Add metal layer 1
    * Add a second dielectric (this time it is Intra-Metal dielectric)
    * Make vias through dielectric to connect lower metal with higher metal. Vias filled by Metal CVD process.

        Repeat steps 4-6 to get all metal layers.

    * Add final passivation layer to protect the microchip

Before 1998, practically all chips used aluminum for the metal interconnection layers. [12] The four metals with the highest electrical conductivity are silver with the highest conductivity, then copper, then gold, then aluminum.

As of 2011, many commercial processes support 2 or 3 metal layers; the most layers supported on a commercial process is 11 layers, and 12 layers are expected to be supported soon.[13]

After BEOL there is a "back-end process" (also called post-fab), which is done not in the cleanroom, often by a different company. It includes wafer test, wafer backgrinding, die separation, die tests, IC packaging and final test.

    References

  [1] Karen A. Reinhardt and Werner Kern (2008). Handbook of Silicon Wafer Cleaning Technology (2nd ed.). William Andrew. p. 202. ISBN 978-0-8155-1554-8.