HBM3 Controller

eda2022

General Product Description
The HBM3 Controller (DWC_hbmx_ctl) is a next generation controller optimized for power, latency,
bandwidth, and area, supporting JDES238, January 2022, JEDEC Standard HBM3 DRAMs .
The DWC_hbmx_ctl connects to the HBM3 PHY through an extended DFI 5.0 Interface to create a complete
memory interface solution. The DWC_hbmx_ctl includes software configuration registers, which are
accessed through an AMBA APB V2.0 Specification interface.
The DWC_hbmx_ctl block includes the advanced dynamic memory access command scheduler (for
example, CAM, QoS), memory protocol handler (for example, Refresh, Refresh Management), power saving
capabilities (for example, Self-Refresh, Power Down, DFI low power, Frequency change), Reliability
features (Read/Write DQ parity, CA Parity, Single Error Correction–Double Error Detection Error
Correcting Code (SEC-DED ECC)), PHY management and DRAM maintenance control (Controller update,
PHY update, Controller message, PHY control interface) and pseudo channel support.
The DWC_hbmx_ctl provides intelligent data management between a system-on-chip (SoC) application bus
(AXI, according to Multiport arm ® AMBA® interface, AXI4 AXI™) and HBM3 PHY for a high density
HBM3 SDRAM . The DWC_hbmx_ctl in conjunction with the HBM3 PHY can handle the details of the
JEDEC HBM 3.0 DRAM protocol, allowing the SoC application to accessHBM 3.0 DRAM memory through
standard AXI interface bus read and write requests.
The DWC_hbmx_ctl delivers high bandwidth by intelligently managing read and write requests from the
SoC. It automatically determines how to serve requested transactions, while avoiding starvation of low
priority requests and guaranteeing data coherency . Latency critical transactions can be scheduled with high
priority and each port may be assigned a different priority level. The DWC_hbmx_ctl also offers multiple
automated low-power states with quick exit latencies and several other power reduction features.
The highly configurable DWC_hbmx_ctl enables you to tune system performance according to the types of
traffic indicative for your system, making the controller ideal for a wide range of system architectures.
Configurable parameters include address and data widths, depth of look-ahead in the scheduler, and
multiple reliability, availability, and serviceability (RAS) features including SEC- DED ECC, data scrubbing,
and parity error status and interrupts. Synopsys coreConsultant or coreAssembler tools offer configuration
and RTL source code generation.